Silicon Platform Engineer
E-SpaceSanta Clara, CA
- Role type
- Experienced
- Track
- Hardware
- Pay
- $150k–$220k
- Posted
- · first seen Oct 18, 2026
“E-Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.”
The label is what this posting says; E-Space's USCIS H-1B history is a separate record of petitions the employer has filed, and this posting's own words take precedence over it.
Job description
We are seeking a skilled and driven Silicon Platform Engineer to join the System-on-Chip platform team that works on IP integration, chip-level verification, and firmware development. This is a System-on-Chip design, integration and verification role, working at the intersection of hardware and software. You will shape the platform from IP bring-up through full-chip validation: defining testbenches, authoring test firmware, and implementing critical chip features in silicon. This is a hands-on role with broad impact across the hardware development cycle.
Core Responsibilities
-
IP Integration and Verification
- IP Integration: Evaluate, integrate, and verify IP blocks within the chip, ensuring correct connectivity, configuration, and interoperability across the platform.
- Feature and Module Firmware: Author targeted test firmware to bring up and verify individual IP blocks and hardware features at the module level.
- Subsystem Firmware: Develop subsystem-level test firmware to validate interactions between integrated components and confirm correct system behavior across hardware boundaries.
Testbench Development and Build Flows
- Testbench Infrastructure: Define, implement, and maintain system-level testbenches covering subsystem and full-chip verification scenarios.
- Build Flow Management: Own and manage testbench build flows, ensuring reproducibility, scalability, and integration with the broader verification environment.
Chip Feature Implementation
- Hardware Security: Implement chip-level security features, including secure boot, hardware root of trust, and cryptographic accelerator integration.
- Inter-Subsystem Communication: Define and implement communication fabrics and protocols between chip subsystems, including AMBA-based interconnects (AXI, AHB, APB).
- Power Management: Implement hardware power management features, including power domain control, clock gating, and low-power state transitions.
- Boot Flow and Configuration: Define and implement the chip boot architecture, including reset sequencing, configuration registers, and boot ROM integration.
What you bring to this role:
- Hardware Description Languages: Proficiency in RTL design and verification using SystemVerilog and/or VHDL.
- Verification Methodologies: Experience with UVM or similar structured verification methodologies.
- Firmware Development: Ability to write bare-metal C firmware for hardware bring-up, feature validation, and test automation on embedded targets.
- AMBA Interconnects: Strong knowledge of AMBA protocols (AXI, AHB, APB) and their application in chip integration.
- Chip Architecture: Understanding of subsystem partitioning, memory maps, interrupt routing, and hardware/software interfaces.
- Debugging Tools: Experience with simulation tools (e.g., VCS, Questa, Xcelium) and hardware debug environments (JTAG, logic analyzers, oscilloscopes).
- Scripting: Proficiency in scripting languages such as Python, Tcl, Bash, and Makefiles for build flow automation and test infrastructure.
- Version Control: Expertise with Git or similar version control systems.
Bonus points for the following:
- Experience with ARM Corstone reference designs and Cortex-M or Cortex-A processor integration.
- Familiarity with TrustedFirmware-M, MCUboot, or PSA-certified security architectures.
- Knowledge of embedded security concepts, including cryptographic algorithms and Post-Quantum Cryptography (PQC).
- Experience with formal verification or property checking tools.
- Familiarity with FPGA emulation platforms for pre-silicon validation.
- Knowledge of 3GPP network protocols as they relate to modem or connectivity subsystem integration.
- Experience with low-power chip design and power intent methodologies (UPF/CPF).
- Familiarity with Cortex-A and Cortex-M class processors, NPU processors, and DSP processors.
- Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Collaboration and Documentation:
· Cross-Functional Partnership: Work closely with Silicon firmware engineers, RTL designers, and physical design teams to ensure cohesive hardware-software integration throughout the development cycle.
· Documentation: Produce and maintain clear technical documentation covering integration specifications, verification plans, test procedures, and feature implementation details.
Additional Requirements
Source: jobs.lever.co · E-Space US · Listing c687b07c-2f4f-4ca2-8ea0-06ad313b9ae8
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